The present invention relates to a method of automatically calibrating a phase locked loop (PLL) system, and to a PLL system comprising at least one phase detector cascade connected to a low-pass filter and to a controlled oscillator, as well as to a frequency divider that is feedback connected between the controlled oscillator and the phase detector. The invention relates particularly, but not exclusively, to a method of automatically calibrating a PLL system specifically providing a frequency multiplier function.
A phase locked loop or PLL system, diagrammatically shown in FIG. 1, comprises a phase detector PD, a low-pass filter LPF, and a voltage-controlled oscillator VCO cascade connected together between an input terminal IN and an output terminal OUT of the PLL system.
A conventional PLL system also includes a frequency divider DIV, which is feedback connected between the output terminal OUT and the input terminal IN. In particular, the phase detector PD detects a phase difference between first SREF and second SVCO input signals.
The first input signal SREF is an oscillating signal at a reference frequency FREF, and the second input signal SVCO is an oscillating signal at a feedback frequency FVCO that is derived from an oscillation output frequency FOUT of an output signal SOUT from the controlled oscillator VCO, as suitably divided within the frequency divider DIV. Since a PLL system operates according to the oscillation frequencies of the signals that flow through it, reference will hereinafter be made to frequencies of interest. These frequencies are the oscillation frequencies of corresponding oscillating signals.
The PLL system shown in FIG. 1 further includes a charge pump phase comparator CPPC connected between the phase detector PD and the low-pass filter LPF. In particular, the charge pump phase comparator CPPC allows a charge stored in a capacitor, provided in the low-pass filter LPF, to be injected, removed, or left unchanged as may be controlled by first UP and second DOWN output signals from the phase detector PD. These output signals UP and DOWN have pulses that are related to the amount of shift that exists between the input frequencies FREF and FVCO to the phase detector PD, as diagrammatically shown in FIG. 2.
The low-pass filter LPF is used to extract an average value from an output voltage signal VLPF from the charge pump phase comparator CPPC. This is done so that a voltage signal VVCO can be input to the controlled oscillator VCO and a desired frequency can be obtained.
To further clarify operation of the PLL system, reference will now be made to FIG. 3, which shows a portion of the PLL system of FIG. 1 in greater detail. In particular, FIG. 3 shows a circuit structure 1, which corresponds to a combination of the charge pump phase comparator CPPC, the low-pass filter LPF, and the controlled oscillator VCO in the PLL system of FIG. 1.
The circuit structure 1 comprises an operational amplifier 2 having a first input terminal IN1 connected to a first internal circuit node X1 of the circuit structure 1. This node is connected to a supply voltage reference Vcc through a control resistive element RVCO. A second input terminal IN2 is connected to a second internal circuit node X2. More specifically, this node is intermediate first G1 and second G2 generators supplying a reference current Iref. These generators are connected in series with each other between the supply voltage reference Vcc and a second voltage reference. The second voltage reference is specifically a ground reference GND. The circuit structure 1 further includes an output terminal OUT1 connected to a control terminal of an output transistor MOUT. The output transistor MOUT is connected between the first internal circuit node X1 and the controlled oscillator VCO.
The first and second generators G1 and G2 are connected to the second internal circuit node X2 through first SW1 and second SW2 electronic switches that are respectively driven by the output signals UP and DOWN from the phase detector PD. The output transistor MOUT drives the controlled oscillator VCO by supplying it with a regulating current IVCO.
The circuit structure 1 additionally comprises a first filtering capacitor Cf1 and a filtering resistive element Rf, which are connected in series with each other, between the second input terminal IN2 of the operational amplifier 2 and ground GND. A second filtering capacitor Cf2 is connected to a point intermediate the first filtering capacitor Cf1 and the filtering resistive element Rf, as well as to ground GND.
The size of the low-pass filter LPF is set by adjustment of the values of the first and second capacitors Cf1 and Cf2, and the value of the filtering resistive element Rf. In particular, to obtain a damping factor (which is one of the characterizing parameters of a system dynamic response) such that the transient of the PLL system can be fast and does not show any overshoots, filter elements can be used that have the following values: Cf1=1 nF; Rf=76 kxcexa9; and Cf2=200 pF.
In this way, a damping factor of approximately 0.7 is obtained. This is regarded as an optimum value for closed-loop systems. Because of its size, the first filtering capacitor Cf1 cannot be integrated to the remainder of the PLL system, and is provided externally. The second filtering capacitor Cf2 reduces spikes in the control voltage VLPF waveform at the second internal circuit node X2. The spikes originate from switching of the switches SW1 and SW2.
The output voltage VVCO from the low-pass filter LPF controls the regulating current IVCO to the controlled oscillator VCO. This is done through the regulating resistive element RVCO connected between the supply voltage reference Vcc and the first internal circuit node X1.
It is readily known that a voltage controlled oscillator VCO can be formed by a series of variable-current inverters connected into a loop and having capacitors interposed therebetween. The VCO outputs a signal SOUT whose oscillation frequency FOUT is tied to the input current IVCO.
The operation of the subject PLL system will be better explained by considering the illustrative case of a pulse in the first output signal UP received at a given time from the phase detector PD. This implies that the feedback frequency FVCO from the frequency divider DIV is late on the reference frequency FREF. In this case, the charge pump phase comparator CPPC will respond by closing the second switch SW2 to ground GND. This causes the charge stored in the first filtering capacitor Cf1 to be diminished.
In this way, an increase in the input current IVCO to the controlled oscillator VCO is obtained, which produces an increase in the output frequency FOUT, and accordingly, brings the feedback frequency FVCO back into phase with the reference frequency FREF. The frequency divider DIV in the feedback leg turns the PLL system into a frequency multiplier by a multiplication factor N. In several applications, e.g., hard-disk noise compensation using an accelerometer and feed-forward compensation techniques, the multiplication factor N to be used is fairly large, and the operating frequency range that is possible for the PLL system becomes wide.
By way of example and not to be a limitation, in case of a hard-disk control, the frequency values and multiplication factors may be: FREF: 5 to 30 kHz; and FCVO: 1.12 to 6.72 MHz with N=224. Setting such values makes for more complicated sizing of the PLL system components. In particular, to obtain all the desired frequencies, the input current IVCO to the controlled oscillator VCO is forced to values that are incompatible with the current values through the remainder of the PLL system.
It can be shown that the following relation applies to a PLL system like that illustrated by FIGS. 1 and 3:                                           F            VCO                                F            REF                          =                              (                          1              +                              sRfCf                ⁢                                  xe2x80x83                                ⁢                1                                      )                                1            +                          sRfC              ⁢                              xe2x80x83                            ⁢              1                        +                                                            s                  2                                ⁢                Cf                ⁢                                  xe2x80x83                                ⁢                1                ⁢                                  R                  VCO                                                            KdK                VCO                                                                        (        1        )            
where       Kd    =          Irif              2        ⁢        π              ,
and Irif is the current from the generators G1 and G2. The calibration parameters for the PLL system can be obtained from relation (1) above, as follows:                               ω          n                =                                            Irif                              Cf                ⁢                                  xe2x80x83                                ⁢                1                ⁢                                  R                  VCO                                                      ⁢                                          K                VCO                                            2                ⁢                π                ⁢                                  xe2x80x83                                ⁢                N                                                                        (        2        )                                ξ        =                                            ω              n                        ⁢            RfCf            ⁢                          xe2x80x83                        ⁢            1                    2                                    (        3        )            
where KVCO*IVCO is the transfer function of the controlled oscillator VCO.
In a real application, all of the parameters found would be subject to appropriate specifications. In particular, the following set of conditions is obtained:                                                                                                               ω                    n                                    =                                                                                                              Irif                                                      CfR                            VCO                                                                          ⁢                                                                              K                            VCO                                                                                2                            ⁢                            π                            ⁢                                                          xe2x80x83                                                        ⁢                            N                                                                                                                =                                          21                      ⁢                                              Krad                        s                                                                                                                                                                  ζ                  =                                                                                                              ω                          n                                                ⁢                        RfCf                        ⁢                                                  xe2x80x83                                                ⁢                        1                                            2                                        =                    0.7                                                                                                                        1                   less than                                       V                    X1                                     less than                                       4                    ⁢                    V                                                                                                                                            K                    VCO                                    =                                      2.9                    ⁢                                          E                      10                                        ⁢                    H                    ⁢                                          xe2x80x83                                        ⁢                                                                  H                        ⁢                                                  xe2x80x83                                                ⁢                        z                                            A                                                                                                    }                ⇔                  (                                                                      Irif                  =                                      150                    ⁢                                          xe2x80x83                                        ⁢                    uA                                                                                                                                            Cf                    ⁢                                          xe2x80x83                                        ⁢                    1                                    =                                      1                    ⁢                                          xe2x80x83                                        ⁢                    n                    ⁢                                          xe2x80x83                                        ⁢                    F                                                                                                                        Rf                  =                                      76                    ⁢                                          xe2x80x83                                        ⁢                    k                    ⁢                                          xe2x80x83                                        ⁢                    Ω                                                                                                                                            R                    VCO                                    =                                      7                    ⁢                                          xe2x80x83                                        ⁢                    k                    ⁢                                          xe2x80x83                                        ⁢                    Ω                                                                                )                                    (        4        )            
wherein the value of a voltage VX1 at the first internal circuit node X1 is enforced by the need to have the low-pass filter LPF correctly biased. This is also in view of the fact that values below the lowest limit and above the highest limit can be reached during the transient. The value of KVCO is a design setting based on a relation KVCO=SOUT/IVCO.
At a value of xcfx89n equal to 21 Krad/s (which is a plausible value in applications such as those under consideration), and a resistance RVCO of 7 kxcexa9, the following approaches are obtained in the frequency range sought: at FREF=30 kHz, and IVCO=(FOUT/KVCO)=231 uA. Therefore, VX1=3.38V within the above set limits, however: at FREF=5 kHz, and IVCO=(FOUT/KVCO)=38 uA. Therefore, VX1=4.73V is outside the above set limits.
Thus, at the frequency range of interest, the values found for the voltage VX1 fall outside the limits set by the above relation (4). It should be noted that, not even by reducing the value of xcfx89n down to 15 Krad/s (thus restricting the overall system performance), and accordingly using a resistance RVCO of 21 kxcexa9, can values of the control voltage VVCO be obtained within the allowed range. In particular, at FREF=30 kHz, IVCO=(FOUT/KVCO)=231 uA. Therefore, VX1=0.15V is outside the set limits, and at FREF=5 kHz, IVCO=(FOUT/KVCO)=38 uA. Therefore, VX1=4.2V, is also outside the set limits.
Thus, with a traditional PLL system, no correct value of the control resistive element RVCO can be obtained within the operating frequency range of the PLL system. In addition, the assumed frequency range (5 to 30 kHz) is bound to be extended in future applications involving higher and higher performance levels.
The above-outlined approach is made worse by the fact that the operating frequency range is extended as the multiplication factor N of the PLL system varies. An external element may be provided for selecting each time the reference frequency range that is to be used, thereby calibrating the PLL system. For example, U.S. Pat. No. 6,057,739 to Crowly et al. discloses a PLL system that includes a register whose bits are used to vary the system parameters, and accordingly, the operating range. It should be noted, however, that the write operation into the register is performed externally, and thus it is not automatic.
The underlying technical problem of this invention is to provide a method of automatically calibrating a PLL system such that the PLL system can automatically match any range of operating frequencies, thereby overcoming the limitations and obviating the drawbacks of known PLL systems.
In view of the foregoing background, an object of the present invention is to provide a method of automatically calibrating a PLL system from an estimate of a frequency value of an input signal. The signal is effective to suitably drive switching means provided within the PLL system.
This and other objects, advantages and features in accordance with the present invention are provided by a method of automatically calibrating a phase locked loop (PLL) system comprising the steps of estimating a frequency value of an input signal to the system. Based on the estimated frequency value, a driving signal is generated for a plurality of internal switches provided within the system. The method further includes calibrating the system using the plurality of internal switches driven by the driving signal.
Another aspect of the present invention is directed to a phase locked loop system comprising at least one phase detector cascade connected to a low-pass filter, and to a controlled oscillator. A frequency divider is feedback connected between an output terminal and an input terminal of the PLL system.
The PLL system further comprises an automatic frequency range selecting device connected between the input terminal and an output of the controlled oscillator, and includes at least one controlled variable element connected to a control circuit. The control circuit generates, from a frequency estimate of an input signal presented on the input terminal, a driving signal of the controlled variable element, thereby calibrating the PLL system and automatically matching the system operation to the frequency range of the input signal.